A high-speed low-complexity modified radix-25 FFT processor for gigabit WPAN applications

Abstract— In this paper, we present a novel modified radix-2 algorithm for 512-point fast Fourier transform (FFT) computation and high-speed eight-parallel data-path architecture for multi-gigabit wireless personal area network (WPAN) systems. The proposed FFT processor can provide a high data throughput and low hardware complexity by using eight-parallel data-path and multi-path delay-feedback (MDF) structure. The modified radix-2 FFT algorithm is also realized in our processor to reduce the number of complex multiplications and twiddle factor look-up tables. The proposed FFT processor has been designed and implemented with 90nm CMOS technology in a supply voltage of 1.2V. The proposed 512-point modified radix-2 FFT/IFFT processor has a throughput rate of up to 2.8 GS/s at 350 MHz while requiring much smaller hardware complexity and low power consumption.